H. Balachandran, Y. J. Kwon, and D. M. H. Walker, "IDDQ Current Calibration with Process Variations", IEEE Int'l Workshop on IDDQ Testing, Oct. 1995.
H. Balachandran, and D. M. H. Walker, "Improvement of SRAM-based Failure Analysis Using Calibrated IDDQ Testing", IEEE VLSI Test Symposium, May. 1996. [PDF]
B. Choi and D. M. H. Walker, "Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation", IEEE VLSI Test Symposium, Montreal, Canada, April 2000. [
J. Lee, D. M. H. Walker, L. Milor, Y. Peng, and G. Hill, "IC Performance Prediction for Test Cost Reduction", 1999 International Symposium on Semiconductor Manufacturing, Santa Clara, CA, November 1999. [
Y. Liao and D. M. H. Walker, "Fault Coverage Analysis of Physically-Based Bridging Faults at Different Power Supply Voltages", IEEE Int'l Test Conf., Oct. 1996. [
D. Nayak and D. M. H. Walker, "Simulation-Based Design Error Diagnosis and Correction in Combinational Circuits", 1999 VLSI Test Symposium, Dana Point, CA, April 1999, pp. 70-78. [
V. Sar-Dessai and D. M. H. Walker, "Accurate Fault Modeling and Fault Simulation of Resistive Bridges", IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems", Nov. 1998. [
V. Sar-Dessai, and D. M. H. Walker, "Resistive Bridge Fault Modeling, Simulation, and Test Generation", IEEE International Test Conference, September 1999. [
T. A. Unni and D. M. H. Walker, "Model-Based IDDQ Pass/Fail Limit Setting", 1998 IEEE International Workshop on IDDQ Testing, San Jose, CA, November 1998. [PDF]
D. M. H. Walker, "Requirements for Practical IDDQ Testing of Deep Submicron Circuits", IEEE International Workshop on Current and Defect Based Testing, Montreal, Canada, April 2000. [PDF]
L. Zhao, D. M. H. Walker, and F. Lombardi, "Bridging Fault Detection in FPGA Interconnects Using IDDQ", 1998 Sixth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, March 1998, pp. 95-104.
L. Zhao, D. M. H. Walker, and F. Lombardi, "Detection of Bridging Faults in Logic Resources of Configurable FPGAs Using IDDQ", IEEE International Test Conference, Washington, DC, October 1998.
L. Zhao, D. M. H. Walker, and F. Lombardi, "IDDQ Testing of Bridging Faults in Logic Resources of Reprogrammable Field Programmable Gate Arrays", IEEE Trans. on Computers, October 1998, pp. 1136-1152.
S. Balasubramaniam, A. K. Sarwar and D.M.H. Walker. "Yield Learning in Integrated Circuit Package Assembly", IEEE Trans. on Components, Packaging, and Manufacturing, Technology, Part C: Manufacturing, pp. 133-141, April 1997.
Z. Stanojevic, H. Balachandran, D. M. H. Walker, F. Lakhani, S. Jandhyala, J. Saxena and K. M. Butler, "Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis", IEEE International Test Conference, Atlantic City, NJ, October 2000. [
Gaitonde, D.D., and D.M.H. Walker, "Hierarchical Mapping of Spot Defects to Catastrophic Faults Design and Applications," IEEE Trans. on Semiconductor Manufacturing, pp. 167-177, May 1995.
D. D. Gaitonde, J. Khare, D. M. H. Walker and W. Maly "Estimation of Reject Rates in Testing of Combinatorial Circuits", 1993 VLSI Test Symposium, Atlantic City, NJ, April 1993, pp. 319-325. [
S. S. Sabade and D. M. H. Walker "Improved Wafer-levl Spatial Analysis for IDDQ Limit Setting", 2001 International Test Conference, Baltimore, MD, Oct 2001, pp. 82-91. [
S. S. Sabade and H. Walker "Evaluation of Outlier RejectionMethods for IDDQ Limit Setting", 2002 VLSI Design and Asia South Pacific Design Automation Conference, Bangalore, India, Jan 2002. [
S. S. Sabade and D. M. H. Walker "Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejectio-based IDDQ Testing for Burn-in Reduction", 2002 VLSI Test Symposium, Monterey, CA, Apr 2002. [
S. S. Sabade and D. M. H. Walker "Wafer-level Spatial and Flush Delay Correlation Analysis for IDDQ Estimation", 2002 Defect-based Testing Workshop, Monterey, CA, Apr 2002. [
S. S. Sabade and D. M. H. Walker "NCR: A Self-scaling, Self-calibrated Metric for IDDQ Outlier Identification", Midwest Symposium on Circuit and Systems, Tulsa, OK, Aug. 2002. [
S. S. Sabade and D. M. H. Walker "Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis", International Symposium on Defect and Fault Tolerant Systems, Vancouver, Canada, Nov. 2002. [
S. S. Sabade and D. M. H. Walker "Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification," IEEE VLSI Design Conference, New Delhi, India, 2003. [
S. S. Sabade and D. M. H. Walker "IDDQ Test: Will It Survice the DSM Challenge?", IEEE Design & Test of Computers, Special Issue, Sep.-Oct. 2002. Original Draft [
S. S. Sabade and D. M. H. Walker "Use of Multiple IDDQ Test Metrics for Outlier Identification", VLSI Test Symposium, April 2003. [PDF]
S. S. Sabade and D. M. H. Walker "Wafer Signature Analysis of IDDQ Data", 2003 Defect-based Testing Workshop, Napa Valley, CA, Apr 2003. [PDF]
S. S. Sabade and D. M. H. Walker "CROWNE: Current Ratio Outliers With Neighbor Estimator", IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 2003. [PDF]
S. S. Sabade and D. M. H. Walker "Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests", IEEE Intl. Conference on VLSI Design, Jan. 2004. [PDF]
S. S. Sabade and D. M. H. Walker "On Comparison of NCR Effectiveness With a Reduced IDDQ Vector Set", IEEE VLSI Test Symposium, Apr. 2004. [PDF]
S. S. Sabade and D. M. H. Walker "Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR Vs NCR", 2004 Defect-based Testing Workshop, Napa Valley, CA, Apr 2004. [PDF]
S. S. Sabade and D. M. H. Walker "IDDQ Data Analysis Using Neighbor Current Ratios", Journal of System Architecture, Special issue on Design and Test of Systems on a chip, Apr. 2004. [PDF]
Sagar S. Sabade "Leakage Current-based Testing of CMOS ICs", IEEE Potentials, Apr/May. 2004. [PDF]
S. S. Sabade and D. M. H. Walker "IDDX-based Test Methods: A Survey", ACM Transactions on Design Automation of Electronic Systems [PDF]
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