Research Areas

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Research Overview slides

 

 

Real-time Embedded Systems

Real-time scheduling, Slack Management, Power & Reliable-aware scheduling, Energy efficient sensor networks

Research is focused on mobile and wireless networked computing systems, energy-efficient MAC protocols and secure routing in wireless sensor network. Current research focuses on deploying mobile agents in a sensor field to collects sensor data and minimizes energy consumption in the static nodes. We also investigate the security issues in wireless sensor network with mobile agents.

 

Semantic Cyberinfrastructures & Cyber Physical Systems

In this area, one of our focus is to design systems and underlying architectural components which will make meaningful cyber infrastructures possible. One of the areas which we are currently investigating is Semantic Routed Network. We are working on a networking technology that will allow users to access network resources based on user's intention, instead of using IP addresses. Users will communicate their intentions using meaningful semantic keys (may be keywords in simple situations) that best describe the network resource (data, service or a sensor)being looked for. The Semantic Routed Network will route messages and "call back" requests to the resource(s) that best match the semantic key declared by the user. The resource being searched will respond back to the user. Interchangeability of semantic keys will be allowed as long as they convey the same meaning or describe the same resource. By this way users will be able to access existing data repositories, complex sensors and other network resources using interchangeable keys, instead of needing to know their exact locations (IP addresses) or search the network resources with exact matching keys that describe the network resources using centralized directories that normally do not tolerate interchangeability of keys. This will help many applications like bioinformatics, earth and atmospheric sciences, web enablement of sensor networks, etc. This will obviate manual cataloging, indexing and data curation effort in application domains where large volumes of data exists. By developing this technology we intend to create a critical demand for these data and sensors which are not readily accessible to general public today, especially those who do not have the technical expertise to utilize them. This technology will make these large volumes of data and sensor network technologies accessible to users over web. This will push envelope of the sensor network technologies. Here we are investigating semantic routers, service layer, platforms, services, semantic routing models.

Other areas which we are also investigating are: uncertainty issues due to complex hardware & software systems. Safety nets and infrastructure to verify complex HW and SW, etc."

 

System-on-a-Chip

Network-on-Chip (NoC), Multiprocessor SoCs (MPSoCs).

NoCs have been proposed to replace traditional bus-based communication infrastructures. Deployment of these into SoCs require the addressing of issues such as IP core interfacing, reliable on-chip communication and peak power aware on-chip communication. On-line testing of SoCs is a critical challenge for future designs and is an area of investigation.

Power-Aware Fault-Tolerance in Real-Time Multiprocessor Systems focuses on using stochastic fault bounds to optimize the level of fault-tolerance needed for the system. As a first step towards achieving this research goal, we have developed and implemented algorithms to optimally map applications along with replications in order to reduce the overall power consumption. Following up on this, we have developed a three-step approach which provides a stochastic algorithm for replicating tasks, mapping them optimally and run-time replication routine for any faults that might occur beyond the predicted fault bounds.

 

Network Processing Architectures

Architectures for IP Lookup, TCAM based routers, Bloom filters and Hybrid Architecture for IP Lookup.

 

Reconfigurable Architectures

Low Power techniques, FPGA Architecture.

With the growing request of high quality multimedia service, especially in embedded systems, efficient algorithms for audio and/or video data processing have been developed. These algorithms have the characteristics of high complexity data-intensive computation. For these applications, there exist two extreme implementations. One is software implementation running on a general purpose processor and the other is hardware implementation in the form of ASIC. In the first case, it is flexible enough to support various applications but may not yield sufficient performance to cope with the complexity of application. In the second case, we can optimize it better in respect of both power and performance but only for a specific application. Reconfigurable architecture fills the gap between the two approaches, providing higher performance than software implementation and wider applicability than hardware implementation. In this research, we are analyzing the characteristics of embedded applications and taking a look at various design optimizations and methodologies of reconfigurable architecture for embedded applications. This work is being targeted to real implementation of reconfigurable architecture optimized for low power and high speed.