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Recent Publications By Year View by Research Area

2008

  1. Amar Rasheed and Rabi mahapatra, "An Efficient Key Distribution Scheme for Establishing pair-wise keys with a Mobile Sink in Distributed Sensor Networks," to appear in the Proceedings of 7th IEEE Intl. Symposium on Network Computing and Applications 2008.
  2. Yoonjin Kim and Rabi N. Mahapatra, "New Array Fabric for Coarse-Grained Reconfigurable Architecture", To appear in Proceedings of EuroMicro Conference on Digital System Design, 2008.
  3. A. Biswas, S. Mohan and R. Mahapatra, "Optimization of Semantic Routing Table", Accepted for publication in the Proceedings of 17th International Conference on Computer Communications and Networks, 2008
  4. S. K. Mandal, R. N. Mahapatra, "PowerAntz: Distributed Power Sharing Strategy for Network on Chip”, To appear in Proceedings of International Symposium on Low Power Electronic Design, 2008
  5. J. D. Lee and R. Mahapatra, "Distributed Test Vector Storage for Safety-Critical NoC-based Systems", Accepted for publication in the Proceedings of IEEE Workshop on UCAS-4, 2008.
  6. Y. Kim, R. Mahapatra, I. Park and K. Choi, "Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture", Accepted for publication in IEEE Transactions on VLSI Systems.
  7. R. Sridharan, N. Gupta and R. Mahapatra, "Feedback Controlled Fault-tolerant Dynamic Scheduling for Real-time Embedded Applications", to appear in the Proceedings of ACM/IEEE Design Automation Conference (DAC), 2008. [PDF]
  8. S. Mandal, P. Bhojwani, S. Mohanty, and R. Mahapatra, "IntellBatt: Towards Smarter Battery Design", to appear in the Proceedings of ACM/IEEE Design Automation Conference (DAC), 2008.
  9.  D. Dechev, R. Mahapatra, B. Stroustrup, and D. Wagner, " C++ Dynamic Cast in Autonomous Space Systems", to appear in the Proceedings of IEEE ISORC 2008.
  10. H, Yu and R. Mahapatra, "A Space- and Time-Efficient Hash Table Hierarchically Indexed by  Bloom Filters", to appear in Intl. Symposium on Parallel Distributed Systems (IPDPS), 2008.
  11. H. Yu, and R. Mahapatra, "A Memory Efficient Hashing by Multi-predicate Bloom Filters for Packet Classifications", to appear in the Proceedings of Infocom 2008.
  12. J. D. Lee, P. Bhojwani and R. Mahapatra,"An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems," to appear in the Proceedings of IEEE Intl. Symposium for Quality Electronic Design (ISQED) 2008.
  13. Y. Kim and R. Mahapatra, "Reusable Context Pipelining for Low Power Coarse-Grained Reconfigurable Architecture," to be presented in RAW 2008.
  14. R. Samanta, J. Surprise and R. Mahapatra, "Dynamic Aggregation of Virtual Addresses in TLB using TCAM Cells," to appear in Proceedings of ACM/IEEE Intl. Conference on VLSI Design, January 2008.

2007

  1. P. Bhojwani and Rabi Mahapatra, "Robust Concurrent On-Line Testing Network-on-Chip of SoCs", IEEE Transactions on VLSI Systems, Accepted for publication.
  2. S. Acharya and R. Mahapatra, “A Dynamic Slack Management Technique for Real-Time Distributed Embedded System,” IEEE Transactions on Computers, Accepted for Publication, to appear in 2007.
  3. R. Singhal, G. Choi and R. Mahapatra, “Data Handling Limits of On-Chip Interconnects,” IEEE Transactions on VLSI, Accepted for Publication.
  4. Mark Nolen and R. Mahapatra, “A Time Division Multiplexed Test Delivery Methodology for Network-on-Chip Systems,” IEEE D&T, Accepted for Publication.
  5. S. P Mohanty, E. Kougianos and R. Mahapatra, "Hardware Assisted Watermarking for Multimedia," Special Issue on Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia,  International Journal of Computers and Electrical Engineering (Elsevier Ltd.), accepted for publication.
  6. Yoonjin Kim and Rabi N. Mahapatra, "Dynamically Compressible Context Architecture for Low Power Coarse-Grained Reconfigurable Array", to appear in Proceedings of IEEE Intl. Conference on Computer Design (ICCD), Oct. 2007.
  7. P. Bhojwani, J. D. Lee and Rabi Mahapatra, "SAPP: Scalable and Adaptable Peak Power Management in NoCs", to appear in Proceedings of Intl. Symposium on Low Power Electronic Devices (ISLPED), August 2007.
  8. P. Bhojwani and Rabi Mahapatra, "A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip", Proceedings of ACM/IEEE Design Automation Conference (DAC), 2007. (Acceptance rate 25%, ~800 submissions)
  9. P. Bhojwani and Rabi Mahapatra, "An Infrastructure-IP for online testing of network-on-chip based SoCs", Proceedings of IEEE Intl. Symposium for Quality Electronic Design (ISQED), 2007.(Acceptance rate ~30%, 300+ submissions).
  10. Ranjani Sridharan and Rabi Mahapatra, "Analysis of Real-time Embedded Applications in the Presence of Stochastic Fault Model," Proceedings of ACM/IEEE Intl. Conference on VLSI Design, 2007.
  11. Rupak Samanta and Rabi Mahapatra, "An Enhanced CAM Architecture to Acclerate LZW Compression," Proceedings of ACM/IEEE Intl. Conference on VLSI Design, 2007.
  12. R. Singhal, S. Chang, G. Choi, and R. Mahapatra, "Error Control Coding for Combinatorial Circuits based on Output Delay Correlation", Accepted for Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2007.
  13. S. P. Mohanty, E. Kougianos, and R. Mahapatra, “A Comparative Analysis of Gate Leakage and Performance of High-K Nanoscale CMOS Logic Gates,” in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), 2007.
  14. A. Rasheed and R. Mahapatra, "An Energy-Efficient Hybrid Data Collection Scheme in Wireless Sensor Networks," Proceedings of IEEE Intl. Conference on Intelligence Sensors, Sensor Networks and Information Processing (ISSNIP), Dec 2007, Accepted for Publication.
  15. J. D. Lee, P. Bhojwani and R. Mahapatra, "A Framework for Microprocessor Evaluation," Proceedings of 10th IEEE High assurance System engineering symposium, Nov 2007, Accepted for Publication.
  16. J. Lee, P. Bhojwani, R. Mahapatra, "On-line Health Monitoring via Statistical Clustering of On-chip Communication", IEEE Workshop on Diagnostic Services in Network-on-Chips, DATE 2007, pp. 325-326.

2006

  1. A. Rajaram, J. Hu, W. Guo, R. Mahapatra and B. Lu, “Analytical Bound for Unwanted Clock Skew Due to Wire Width Variation,” IEEE Transactions on CAD, .25(9): 1869-1876 (2006).
  2. A. Rajaram, J. Hu, R. Mahapatra, "Reducing Clock Skew Variability via Cross Links", IEEE Transactions on CAD. 25(6): 1176-1182, June 2006.
  3. D. Wu, J. Hu and R. Mahapatra, “Antenna Avoidance in Layer Assignment”, to appear in IEEE Transactions on Computer Aided Design, pp. 734-738, April 2006.
  4. V. Kappagantula, S. Acharya and R. Mahapatra, "A partitioning Algorithm for Power Constrained Reconfigurable Real-Time System", Microprocessors and Microsystems Journal, Accepted for Publication, (Editor: Iain Bate).
  5. Rohit Singhal, Gwan Choi, and Rabi Mahapatra, "Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects," Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD)  2006.
  6. P. Bhojwani and R. Mahapatra, "Core Network Interface Architecture and Latency Constrained On-Chip Communication", in IEEE Symposium on Quality Electronic Design, 2006 (ISQED),pp.358-363 .
  7. R. Singhal, G. Choi and R. Mahapatra, " Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk", Proceedings of  IEEE Symposium on Quality Electronic Design, 2006 (ISQED),pp..407-412 (Acceptance rate 40%)
  8. R. Singhal, G. Choi and R. Mahapatra, "Programmable LDPC Decoder Based on the Bubble-Sort Algorithm," Accepted for Publication in Proceedings of ACM/IEEE International Conference on VLSI Design 2006.
  9. D. Wu, G. Venkataraman, J. Hu, Q. Li, and R. Mahapatra, "DiCER: Distributed and Cost-Effective Redundancy for Variation Tolerance," Accepted for Publication in Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD)  2005. (Acceptance rate 25%)
  10. A. Biswas and R. Mahapatra," Managing Confidence and Reliability in Complex Software Systems with an Adaptive System Monitor", NSF Workshop on High-Confidence Software Platforms for Cyber-Physical Systems (HCSP-CPS), Virginia , Nov 2006.
  11. P. Bhojwani, R. Singhal, G. Choi, R. Mahapatra, "Forward Error Correction for On-chip Interconnection Networks", Proceedings of International Workshop on Unique Chips and Systems (UCAS-II) 2006.

2005

  1. A. Kumar and R. Mahapatra "An Integrated Scheduling and Buffer Management Scheme for Input Queued Switches with Finite Buffer Space", Computers and Communication Journal, Elsevier Publications, Volume 29, Issue 1, pp. 42-51, December 2005.
  2. S. Ahmad and R. Mahapatra, "An Efficient Approach to On-chip Logic Minimization", IEEE Transactions on VLSI, Accepted for Publication, November 2005.
  3. V. C. Ravikumar, R. Mahapatra and L. N Bhuyan, “EaseCAM: An Energy and Storage Efficient TCAM-based Router Architecture”, IEEE Transactions on Computers, Vol.54, No.5, May 2005 pp.521-533.
  4. R. Mahapatra and W. Zhao., "An Energy efficient Slack Distribution Technique for Multimode Distributed Real-time embedded Systems", IEEE Transactions on Parallel and Distributed Systems Volume 16,  Issue 7,  July 2005 pp.650 - 662.
  5. K. Padhi and R. Mahapatra, "A Technique for Identification of Voice in Stereo Soundtracks, "Accepted for Publication in Proceedings of IEEE International Conference on Information, Communications and Signal Processing (ICICS 2005).
  6. S. Ahmad, N. Jayakumar, S. Khatri and R. Mahapatra, “X-Routing using Two Manhattan Routing Instances,” Accepted for Publication in Proceedings of IEEE International Conference on Computer Design (ICCD) 2005.
  7. S. Ahmad and R. Mahapatra, “TCAM Enabled On-Chip Logic Minimization”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2005). (Acceptance rate 20%).
  8. D. Wu, J. Hu and R. Mahapatra, “Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment”, Proceedings of ACM Intl. Symposium on Physical Design (ISPD), 2005. (Acceptance rate: 32%).
  9. A. Kumar and R. Mahapatra, "Integrated Scheduling and Buffer Management Scheme for Input Queued Switches with Extreme Traffic Conditions", Proceedings of IEEE International Conference on Computer Communication (ICC) 2005. (Acceptance rate 34%).
  10. V. Rai and R. Mahapatra, "Lifetime Modeling of a Sensor Network", IEEE Intl. Conf. on Design, Automation and Test in Europe (DATE) 2005. (Acceptance rate 25%).
  11. D. Wu, J. Hu, M. Zhao and R. Mahapatra, "Timing Driven Track Routing Considering coupling Capacitance", Proceedings of  IEEE Intl. Conference on ASP-DAC 2005 (Acceptance rate 40%).
  12. R. Singhal, G. Choi and R. Mahapatra, “Quantized LDPC Decoder Design for Binary Symmetric Channels”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2005.
  13. P. S. Bhojwani, R. Mahapatra, E. J. Kim and T. Chen; "A Heuristic for Peak Power Constrained Design of Network on Chip (NoC) based Multimode Systems", IEEE Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2005, pp.124-129. (Acceptance rate 27.5% out of 352 submissions).
  14. A. Chousein and R. Mahapatra, "Fully Associative Cache Partitioning with Don't Care Bits for Real-time Applications", 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), March 2005. (Also appear as on-line journal article in SIGBED Review, Volume 2, Number 2, April 2005).
  15. M. Nolan and R. Mahapatra, "A TDM Test Scheduling Method for Network-on-Chip Systems," to be presented in IEEE International Workshop on Microprocessor Verification & Testing (MTV) 2005.
  16. H. Kim, E. J. Kim and R. Mahapatra, "Power Management in RAID Server Disk System Using Multiple Idle States", Proceedings of International Workshop on Unique Chips and Systems (UCAS) 2005.
  17. N. Goyal and R. Mahapatra "Energy Characterization of CRAMFS for Embedded Systems", International Workshop on Software Support for Portable Storage (IWSSPS), March 2005.

2004

  1. V. C. Ravikumar, and R. Mahapatra, “Ternary-CAM Architecture for IP Lookup Using Prefix Properties”, IEEE Micro, April/May 2004, pp.60-69.
  2. S. Ahmad and R. Mahapatra, "m-Trie: An Efficient Approach to On-chip Logic Minimization", Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2004, pp.428-435. (Acceptance rate 24%).
  3. S. Choudhuri and R. Mahapatra, “Energy Characterization of File Systems for Diskless Embedded Systems”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2004), pp.566-469. (Acceptance rate 25%).
  4. A. Rajaram, J. Hu and R. Mahapatra, “Reduced Clock Skew Variability via Cross Links”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2004) pp. 18-23. (Acceptance rate 25%, Nominated for best paper award).
  5. D.  Wu, J. Hu, R. Mahapatra and M. Zhao, “Layer assignment for Crosstalk Risk Minimization”, Proceedings of  IEEE Intl. Conference ASP-DAC 2004, pp. 159-162, (Acceptance rate 50%).

2003

  1. A. Rajaram, W. Guo, B. Lu, R. Mahapatra and J. Hu, "Analytical Bound for Unwanted Clock Skew due to Wire Width Variation”, Proceedings of IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2003, pp. 401-407(Acceptance rate 25%).
  2. P. Bhojwani and R. Mahapatra, “Interfacing Cores with On-chip Packet-Switched Networks”, IEEE Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2003, (Acceptance rate 39%).
  3. K. Pramod and R. Mahapatra, “PAP: Power Aware Partitioning of Reconfigurable Systems”, HPCA Workshop on SSRS, Anaheim, CA, Feb. 8, 2003.
  4. M. Satpathy, R. Mahapatra, S Choudhuri and S. V. Chintis, “High performance code generation through lazy activation records”, Interaction Between Compilers and Computer Architectures, 2003. INTERACT-7 2003. Proceedings. Seventh Workshop on 8 Feb. 2003 Page(s):37 - 47, (Acceptance rate 50%).

2002 and Earlier

  1. A. Prasad, W. Qui and R. Mahapatra, “Hardware Software Partitioning of Multifunction Systems” Proceedings of Intl. Conf. on Information Technology, India, Dec 2002 (Acceptance rate 25%).
  2. V C Ravikumar, R. Mahapatra, J.C Liu, “Modified LC-Trie based Efficient Routing Look Up”, IEEE/ACM Proceedings on MASCOTS, October 2002, (Acceptance rate 30%).
  3. M. Pirvu, Laxmi Bhuyan and R. Mahapatra, “Hierarchical Simulation of a Multiprocessor Architecture", Proceedings, Intl. Conference on Computer Design (ICCD), October 2000.
  4. N. Subramanian, S. Pandita and R. Mahapatra, “Co-Design of Reactive Embedded System for Motion Control in Hostile Environment”, 8th IAPR workshop on Machine Vision Applications, Japan, December 2002.
  5. D. Mohanty, R. Mahapatra and G. Choi, “A Design Space Exploration Framework in Multiprocessor SoC Codesign", Proceedings of Workshop on RTSS Embedded Systems, Dec 3, 2001.
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