Recent Publications


 Rabi N Mahapatra

Associate Professor of Computer Science

Texas A&M University

         Refereed Journal Articles

  1. S. Acharya and R. Mahapatra, “A Dynamic Slack Management Technique for Real-Time Distributed Embedded System,” IEEE Transactions on Computers, Accepted for Publication. (Editor: L. Welch).
  2. R. Mahapatra and W. Zhao., "An Energy efficient Slack Distribution Technique for Multimode Distributed Real-time embedded Systems", IEEE Transactions on Parallel and Distributed Systems Volume 16,  Issue 7,  July 2005 pp.650 - 662. (paper)
  3. V. C. Ravikumar, R. Mahapatra and L. N Bhuyan, “EaseCAM: An Energy and Storage Efficient TCAM-based Router Architecture”, IEEE Transactions on Computers, Vol.54, No.5, May 2005 pp.521-533. (paper)
  4. S. Ahmad and R. Mahapatra, "An Efficient Approach to On-chip Logic Minimization", IEEE Transactions on VLSI, Accepted for Publication, November 2005.

  5. D. Wu, J. Hu and R. Mahapatra, “Antenna Avoidance in Layer Assignment”, IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 734-738 (2006).

  6. V. C. Ravikumar, and R. Mahapatra, “Ternary-CAM Architecture for IP Lookup Using Prefix Properties”, IEEE Micro, April/May 2004, pp.60-69. (paper)
  7. A. Rajaram, J. Hu, R. Mahapatra, "Reducing Clock Skew Variability via Cross Links", IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1176-1182 (2006)
  8. A. Kumar and R. Mahapatra "An Integrated Scheduling and Buffer Management Scheme for Input Queued Switches with Finite Buffer Space", Computers and Communication Journal, Elsevier Publications, Volume 29, Issue 1, pp. 42-51. (paper)
  9. A. Rajaram, J. Hu, W. Guo, R. Mahapatra and B. Lu, “Analytical Bound for Unwanted Clock Skew Due to Wire Width Variation,” IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006).

  10. V. Kappagantula, S. Acharya and R. Mahapatra, "A partitioning Algorithm for Power Constrained Reconfigurable Real-Time System", Microprocessors and Microsystems Journal, Accepted for Publication, (Editor: Iain Bate).
     

   Refereed Conference Articles

  1. P. Bhojwani* and R. Mahapatra, "An Infrastructure IP for Online Testing of Network-on-Chip based SoCs", to appear in the Proceedings of IEEE Intl. Symposium on Quality Electronic Design (ISQED), 2007, (Acceptance rate ~30%, 300+ submissions).
  2. R. Sridharan* and Rabi Mahapatra, "Analysis of Real-time Embeddedb Applications in the Presence of Stochastic Fault Model," Proceedings of ACM/IEEE Intl. Conference on VLSI Design, 2007.

  3. R. Samanta* and R. Mahapatra, "An Enhanced CAM Architecture to Acclerate LZW Compression," Proceedings of ACM/IEEE Intl. Conference on VLSI Design, 2007.

  4. R. Singhal*, G. Choi, and R. Mahapatra, "Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects," Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2006.

  5. P. Bhojwani* and R. Mahapatra, "Core Network Interface Architecture and Latency Constrained On-Chip Communication", to appear in IEEE Symposium on Quality Electronic Design, 2006 (ISQED), pp.358-363 .
  6. R. Singhal*, G. Choi and R. Mahapatra, " Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk", to appear in the Proceedings of  IEEE Symposium on Quality Electronic Design", 2006 (ISQED), pp.407-412. (Acceptance rate 40%)
  7. R. Singhal*, G. Choi and R. Mahapatra, "Programmable LDPC Decoder Based on the Bubble-Sort Algorithm," Accepted for Publication in Proceedings of ACM/IEEE International Conference on VLSI Design 2006, pp.203-208.
  8. D. Wu*, G. Venkataraman, J. Hu, Q. Li, and R. Mahapatra, "DiCER: Distributed and Cost-Effective Redundancy for Variation Tolerance," Accepted for Publication in Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD)  2005, 393-397. (Acceptance rate 25%)
  9. K. Padhi* and R. Mahapatra, "A Technique for Identification of Voice in Stereo Soundtracks, "Accepted for Publication in Proceedings of IEEE International Conference on Information, Communications and Signal Processing (ICICS 2005).
  10. S. Ahmad*, N. Jayakumar*, S. Khaitri and R. Mahapatra, “X-Routing using Two Manhattan Routing Instances,” Accepted for Publication in Proceedings of IEEE International Conference on Computer Design (ICCD) 2005, pp.45-52.
  11. S. Ahmad* and R. Mahapatra, “TCAM Enabled On-Chip Logic Minimization”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2005), pp.678-683. (Acceptance rate 20%).(paper)
  12. D. Wu*, J. Hu and R. Mahapatra, “Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment”, Proceedings of ACM Intl. Symposium on Physical Design (ISPD), 2005, pp.20-27. (Acceptance rate: 32%). (paper)
  13. A. Kumar* and R. Mahapatra, "Integrated Scheduling and Buffer Management Scheme for Input Queued Switches with Extreme Traffic Conditions", Proceedings of IEEE International Conference on Computer Communication (ICC) 2005. (Acceptance rate 34%). (paper)
  14. V. Rai* and R. Mahapatra, "Lifetime Modeling of a Sensor Network", IEEE Intl. Conf. on Design, Automation and Test in Europe (DATE) 2005, 202-203. (Acceptance rate 25%). (paper, extended version)
  15. D. Wu*, J. Hu, M. Zhao and R. Mahapatra, "Timing Driven Track Routing Considering coupling Capacitance", Proceedings of  IEEE Intl. Conference on ASP-DAC 2005, pp.1156-1159. (Acceptance rate 40%). (paper)
  16. R. Singhal*, G. Choi and R. Mahapatra, “Quantized LDPC Decoder Design for Binary Symmetric Channels”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2005, pp.5782-5785. (paper)
  17. P. S Bhojwani*, R. Mahapatra, E. J. Kim and T. Chen; "A Heuristic for Peak Power Constrained Design of Network on Chip (NoC) based Multimode Systems", IEEE Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2005, pp.124-129. (Acceptance rate 27.5% out of 352 submissions). (paper)
  18. S. Ahmad* and R. Mahapatra, "m-Trie: An Efficient Approach to On-chip Logic Minimization", Proceedings of ACM/IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2004, pp.428-435. (Acceptance rate 24%). (paper)
  19. S. Choudhuri* and R. Mahapatra, “Energy Characterization of File Systems for Diskless Embedded Systems”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2004), pp.566-469. (Acceptance rate 25%). (paper)
  20. A. Rajaram*, J. Hu and R. Mahapatra, “Reduced Clock Skew Variability via Cross Links”, Proceedings of ACM/IEEE International Design Automation Conference (DAC 2004) pp. 18-23. (Acceptance rate 25%, Nominated for best paper award). (paper)
  21. D.  Wu*, J. Hu, R. Mahapatra and M. Zhao, “Layer assignment for Crosstalk Risk Minimization”, Proceedings of  IEEE Intl. Conference ASP-DAC 2004, pp. 159-162, (Acceptance rate 50%). (paper)
  22. A. Rajaram*, W. Guo, B. Lu, R. Mahapatra and J. Hu, "Analytical Bound for Unwanted Clock Skew due to Wire Width Variation”, Proceedings of IEEE Intl. Conference on Computer-Aided Design (ICCAD) 2003, pp. 401-407(Acceptance rate 25%). (paper)
  23. P. Bhojwani* and R. Mahapatra, “Interfacing Cores with On-chip Packet-Switched Networks”, IEEE Proceedings of Intl. Conf. on VLSI Design, IEEE Computer Press, 2003, (Acceptance rate 39%) . (paper)
  24. A. Prasad*, W. Qui* and R. Mahapatra, “Hardware Software Partitioning of Multifunction Systems” Proceedings of Intl. Conf. on Information Technology, India, Dec 2002 (Acceptance rate 25%). (paper)
  25. V C Ravikumar*, R. Mahapatra, J.C Liu, “Modified LC-Trie based Efficient Routing Look Up”, IEEE/ACM Proceedings on MASCOTS, October 2002, (Acceptance rate 30%). (paper)
  26. M. Pirvu*, Laxmi Bhuyan and R. Mahapatra, “Hierarchical Simulation of a Multiprocessor Architecture", Proceedings, Intl. Conference on Computer Design (ICCD), October 2000. (paper)
  27. A. Chousein* and R. Mahapatra, "Fully Associative Cache Partitioning with Don't Care Bits for Real-time Applications", 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), March 2005. (Also appear as on-line journal article in SIGBED Review, Volume 2, Number 2, April 2005). (paper)


    Refereed Workshop Articles
     
  28. A. Biswas* and R. Mahapatra," Managing Confidence and Reliability in Complex Software Systems with an Adaptive System Monitor", NSF Workshop on High-Confidence Software Platforms for Cyber-Physical Systems (HCSP-CPS), Virginia , Nov 2006.
  29. J. D. Lee*, P. Bhojwani* and R. Mahapatra, "On-Line Health Monitoring via Statistical Clustering of On-Chip Communication", Workshop on Diagnostic Services in Network-on-Chips - Test, Debug, and On-Line Monitoring, ACM/IEEE DATE 2007.
  30. P. Bhojwani*, R. Singhal*, G.  Choi, R. Mahapatra, "Forward Error Correction for On-chip Interconnection Networks", Proceedings of International Workshop on Unique Chips and Systems (UCAS-II) 2006.
  31. M. Nolan* and R. Mahapatra, "A TDM Test Scheduling Method for Network-on-Chip Systems," to be presented in IEEE International Workshop on Microprocessor Verification & Testing (MTV) 2005.
  32. H. Kim*, E. J. Kim and R. Mahapatra, "Power Management in RAID Server Disk System Using Multiple Idle States", Proceedings of International Workshop on Unique Chips and Systems (UCAS-I) 2005. (paper)
  33. N. Goyal* and R. Mahapatra "Energy Characterization of CRAMFS for Embedded Systems", International Workshop on Software Support for Portable Storage (IWSSPS), March 2005. (paper)
  34. K. Pramod* and R. Mahapatra, “PAP: Power Aware Partitioning of Reconfigurable Systems”, HPCA Workshop on SSRS, Anaheim, CA, Feb. 8, 2003. (paper)
  35. M. Satpathy, R. Mahapatra, S Choudhuri* and S. V. Chintis, “High performance code generation through lazy activation records”, Interaction Between Compilers and Computer Architectures, 2003. INTERACT-7 2003. Proceedings. Seventh Workshop on 8 Feb. 2003 Page(s):37 - 47, (Acceptance rate 50%). (paper)
  36. N. Subramanian*, S. Pandita* and R. Mahapatra, “Co-Design of Reactive Embedded System for Motion Control in Hostile Environment”, 8th IAPR workshop on Machine Vision Applications, Japan, December 2002. (paper)
  37. D. Mohanty*, R. Mahapatra and G. Choi, “A Design Space Exploration Framework in Multiprocessor SoC Codesign", Proceedings of Workshop on RTSS Embedded Systems, Dec 3, 2001. (paper)